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DMA Controller

General description Features

The DMA controller can be used to transfer a memory
block from one memory location to another. Currently it supports only
word (= 32 bit) transfers. The bit enblae_dma_done_irq of the CONTROL register allows to issue an interrupt after DMA transfer is finished.

 The DMA controller allows transferring a data blocks from
one memory location to another.
  • Implemented as AHB master
    		•
  • Programmable Transfer Size
    		•
  • Optional Interrupt after Data Transfer
    		•
     
  • Source Address Increment: either +1 Word or No Increment
    		•
     
  • Destination Address Increment: either +1 Word or No Increment

    • Block Diagram

     

    block diagram

     

     

    Device Utilization & Performance

    Technology

    Device

    Utilization

    (Average out of some different applications)

    Performance

    Stratix III

    (Altera)    		 EP3SL150F780

    Logic Elements: 760

    Block Memory: 0

    100 MHz

    AHB bus clock

    ArriaGX

    (Altera)    		 EP1AGX90EF1

    Logic Elements: 760

    Block Memory: 0

    100 MHz

    AHB bus clock


     

     

     

     
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