FPGA Code Protector

Functional Description To protect an IP core, the FPGA Code Protector does not encrypt the configuration file but constantly supervises the design during its operation (see fig. 1). With the aid of a CPLD handshaking tokens are being generated and sent to the components involved. If the tokens are correct, the system clock will be enabled for the user's design allowing it to run. If they are wrong, the clock will remain disabled.
	The combination of a sophisticated random number generator and approved encryption algorithms securely hinders trespassers from acquiring confidential data. The Code Protector is technologically independent. It allows to arbitrarily exchange the CPLD and the FPGA and makes sure you are not bound to one semiconductor manufacturer.
figure 1: security system The FCP is available as a 100-pin TQFP CPLD. The corresponding FPGA security core will be synthesized for your target technology and be provided as a black box. Gleichmann Electronics Research offers it for Altera, Lattice and Xilinx chips at the moment. The FPGA development system Hpe_mini LEC, which is also available from GER ships with the FCP on it. It is ideal for evaluation purposes of the protection system.