| The GERA SPI Master IP-core is a simple SPI master with AHB interface.
For a minimum of SPI functionality 3 wires (SCKL, MOSI, MISO are required. To provide flexibility for more use cases the IP-core offers also a slave select (SSEL) and address outputs to communicate with multiple SPI slaves. Address bit width, word bit width and the buffer FIFO depth can be set by generics. |
- AMBA 2.0 AHB interface
- Generics for
Bit width of address port
Word width of FIFO and shift register
FIFO depth of write and read buffer |
